Electrostatic discharge (ESD) refers to a phenomena wherein a charged device of a given potential suddenly discharges carriers to a separate device of lower potential. The discharge occurs over a short time frame and, therefore, results in a momentarily large current, if the resistance of the discharge path is kept low. The most common example of ESD occurs when a human walks over a carpeted area in low humidity, thereby collecting an electrostatic charge. If the charged human touches a semiconductor device, an electrostatic discharge takes place from the human to elements of the semiconductor device. Such discharges can damage the semiconductor device unless means are provided for clamping the large voltages and diverting the currents resulting from the electrostatic discharge.
FIG. 1 shows a prior art schematic diagram of a typical electrostatic discharge protection circuit for IC input pads. An input pad 101 is provided for interface with the internal circuit 103 of the IC. Disposed between the input pad 101 and the internal circuit 103 are a pMOS 105 and an nMOS 107 which form the primary protection stage. An nMOS 109 serves as a secondary protection stage. The pMOS and nMOS devices have their gate electrodes connected to their sources.
Generally, an ESD pulse will generate a large amount of joule heating within the MOSFET devices. However, deep submicron devices utilize shallow junctions for better short channel effect control, which reduces the joule heating capability. Therefore, in order to reduce the maximum current density and provide a uniform current path, one prior art practice uses an ESD implant to broaden the source/drain profiles. Thus, as can be seen in FIG. 2, a conventional lightly doped drain MOSFET includes a gate 201, sidewall spacers 203, lightly doped drain regions 205, and source and drain implants 207 and 209, respectively. Additionally, an ESD implant 211 is used to broaden the source drain profiles. Typically, the ESD implant 211 is an implant having the same conductivity type of the source and drain, but of lower concentration. Therefore, the ESD implant 211 is a n-type implant and can be, for example, formed by phosphorous implants. Furthermore, although an nMOS device is shown in FIG. 2, a pMOS transistor can be easily formed by reversing the implant types. A more detailed discussion of this prior art may be found in A. Amerasekera and C. Duvvury, "ESD in Silicon Integrated Circuits," John Wiley and Sons, Inc. (1996), at page 180.
In order to provide enough ESD protection, the MOSFETs in FIG. 1 are designed as large width devices. The large width devices are implemented in a parallelized multi-finger gate configuration. The total gate width is about 300 .mu.m, but will depend on device design. Several tradeoffs must be considered to determine the channel length of the MOSFETs. The shorter channel length device has better ESD performance, so that the total required width is smaller than would be required with longer channel length devices.
The major challenges of implementing shorter channel length devices in protection circuits are the controllability of uniformly turning on snapback operation for each gate finger and keeping off-state leakage current to a minimum to reduce power consumption. Therefore, usually designers choose longer channel length devices for the MOSFETs, although they sacrifice layout area. Recently, a circuit design technique referred to as the "gate-coupled technique" was proposed to improve the controllability of uniform turn on snapback operation for each gate finger. See Ming-Dou Ker et al., "Capacitor-Couple ESD Protection Circuit for Deep-Submicron Low-Voltage CMOS", IEEE Trans. on VLSI Systems, Vol. 4, No. 3, p. 307, Sept. 1996. However, this technique also requires more layout area for ESD protection triggering circuits.
Thus, what is needed is a device that can provide good ESD protection with a short channel length, resulting in reduced layout area.